For advanced technology nodes, static consumption of integrated circuits has become a key factor for the microelectronics industry. Circuit energy efficiency is measured in terms of delay performance and consumption. With the increase of physical and environmental parameters, the Fully-Depleted Silicon-on-Insulator technology allows to extend Moore's law in the nanometer domain. In this work, a statistical study of CMOS-FDSOI integrated circuit energy is carried out. Statistical libraries characterizing delay and power of CMOS-FDSOI transistors are presented. Given the advantages of the FDSOI technology, statistical approaches based on the libraries are applied in order to estimate delay and power. Combined analysis of supply voltage and body-bias voltage allows to determine an efficient Delay-Power compromise and to manage circuit energy with a significant gain in CPU time.