Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2018

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

Manu Komalan
  • Function : Author
Oh Hyung Rock
  • Function : Author
Matthias Hartmann
  • Function : Author
Sushil Sakhare
  • Function : Author
Gouri Sankar Kar
  • Function : Author
Arnaud Furnemont
  • Function : Author
Francky Catthoor
  • Function : Author
Sophiane Senni
  • Function : Author
  • PersonId : 1045499
David Novo
Abdoulaye Gamatié
Lionel Torres

Abstract

Current main memory organizations in embedded and mobile application systems are DRAM dominated. The ever-increasing gap between today's processor and memory speeds makes the DRAM subsystem design a major aspect of computer system design. However, the limitations to DRAM scaling and other challenges like refresh provide undesired trade-offs between performance, energy and area to be made by architecture designers. Several emerging NVM options are being explored to at least partly remedy this but today it is very hard to assess the viability of these proposals because the simulations are not fully based on realistic assumptions on the NVM memory technologies and on the system architecture level. In this paper, we propose to use realistic, calibrated STT-MRAM models and a well calibrated cross-layer simulation and exploration framework, named SEAT, to better consider technologies aspects and architecture constraints. We will focus on general purpose/mobile SoC multi-core architectures. We will highlight results for a number of relevant benchmarks, representatives of numerous applications based on actual system architecture. The most energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 27% at the cost of 2x the area and the least energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 8% at the around the same area or lesser when compared to DRAM.
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lirmm-01912824 , version 1 (27-03-2019)

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Manu Komalan, Oh Hyung Rock, Matthias Hartmann, Sushil Sakhare, Christian Tenllado, et al.. Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks. DATE 2018 - 21st Design, Automation and Test in Europe Conference and Exhibition, Mar 2018, Dresden, Germany. pp.103-108, ⟨10.23919/DATE.2018.8341987⟩. ⟨lirmm-01912824⟩
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