Process networks and data-flow graphs are used to capture data-dependencies in computation-intensive embedded systems. Their simplicity allows the computation of static schedules that reduce the dynamic overhead and increase predictability. The resulting schedule is a total ordering of actor computations and communications. It can therefore become an over-specification of the initial system when several schedules are valid. This is particularly the case for multidimensional data-flow applications. We propose a methodology to avoid such an over-specification. We propose to use logical time to capture explicitly all the valid schedules for a given multi-dimensional data-flow model. Then, we show that the proposed approach allows for a progressive and explicit refinement of computation scheduling that also captures constraints imposed by the environment and the execution platform. All this is achieved by using uml marte concepts and the resulting models can be considered for simulation and analysis with existing tools for early design validation. The whole approach is validated on a typical application devoted to radar signal processing.