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Importance of Interconnects: A Technology-System-Level Design Perspective

Jie Liang 1 Aida Todri-Sanial 1
1 SmartIES - Smart Integrated Electronic Systems
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Current technology-design optimization methodology focuses first on front-end devices and logic gates and then addresses back-end interconnects. But, such approach is no longer feasible for sub-nanometer technologies. Here, we present a circuit-level study where both devices and interconnects are co-optimized to improve energy efficiency. We investigate advanced CMOS technology with 7 nm FinFET devices, and Cu interconnects with various aspect ratios from 3, 5 to 10. Further, we explore the advantages of carbon nanotube (CNT) based circuits with CNT field-effect devices and interconnects. CNT technology can achieve better energy-delay-product with co-exploring front- and back-end co-optimization and paving the way for an intelligent circuit-/system-level design and technology co-optimization.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-02388007
Contributor : Aida Todri-Sanial <>
Submitted on : Thursday, December 12, 2019 - 7:04:04 AM
Last modification on : Thursday, December 12, 2019 - 10:18:23 AM
Long-term archiving on: : Friday, March 13, 2020 - 2:38:40 PM

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  • HAL Id : lirmm-02388007, version 1

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Jie Liang, Aida Todri-Sanial. Importance of Interconnects: A Technology-System-Level Design Perspective. 65th International Electron Device Meeting (IEDM), Dec 2019, San Francisco, United States. ⟨lirmm-02388007⟩

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