Is aproximate computing suitable for selective hardening of arithmetic circuits? - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2018

Is aproximate computing suitable for selective hardening of arithmetic circuits?

Abstract

Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. In this paper, we address the problem of selective hardening of arithmetic circuits by considering a duplication/comparison scheme as error detection architecture. Different duplication scenarios have been investigated: i) a full duplication, ii) a reduced duplication based on a structural susceptibility analysis, iii) a reduced duplication based on the logical weight of the arithmetic circuit outputs and iv) a reduced duplication based on an approximated structure from a public benchmark suite. Experimental results performed on adder and multiplier case study circuits demonstrate the interest of using approximate circuits to improve the mean time to failure while keeping a low area and power overhead and reduced error probability and error magnitude.
Fichier principal
Vignette du fichier
08368559.pdf (999.55 Ko) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

lirmm-03130537 , version 1 (05-02-2021)

Identifiers

Cite

Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman. Is aproximate computing suitable for selective hardening of arithmetic circuits?. DTIS 2018 - 13th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, Apr 2018, Taormina, Italy. pp.1-6, ⟨10.1109/DTIS.2018.8368559⟩. ⟨lirmm-03130537⟩
53 View
87 Download

Altmetric

Share

Gmail Facebook X LinkedIn More