Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. In this paper, we address the problem of selective hardening of arithmetic circuits by considering a duplication/comparison scheme as error detection architecture. Different duplication scenarios have been investigated: i) a full duplication, ii) a reduced duplication based on a structural susceptibility analysis, iii) a reduced duplication based on the logical weight of the arithmetic circuit outputs and iv) a reduced duplication based on an approximated structure from a public benchmark suite. Experimental results performed on adder and multiplier case study circuits demonstrate the interest of using approximate circuits to improve the mean time to failure while keeping a low area and power overhead and reduced error probability and error magnitude.