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Is aproximate computing suitable for selective hardening of arithmetic circuits?

Bastien Deveautour 1 Arnaud Virazel 1 Patrick Girard 1 Serge Pravossoudovitch 1 Valentin Gherman 2
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LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. In this paper, we address the problem of selective hardening of arithmetic circuits by considering a duplication/comparison scheme as error detection architecture. Different duplication scenarios have been investigated: i) a full duplication, ii) a reduced duplication based on a structural susceptibility analysis, iii) a reduced duplication based on the logical weight of the arithmetic circuit outputs and iv) a reduced duplication based on an approximated structure from a public benchmark suite. Experimental results performed on adder and multiplier case study circuits demonstrate the interest of using approximate circuits to improve the mean time to failure while keeping a low area and power overhead and reduced error probability and error magnitude.
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Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman. Is aproximate computing suitable for selective hardening of arithmetic circuits?. 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), Apr 2018, Taormina, Italy. pp.1-6, ⟨10.1109/DTIS.2018.8368559⟩. ⟨lirmm-03130537⟩

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