A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2022

A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology

Aibin Yan
Zhen Zhou
  • Function : Author
  • PersonId : 1161770
Shaojie Wei
  • Function : Author
  • PersonId : 1161771
Jie Cui
Yong Zhou
  • Function : Author
  • PersonId : 1161772
Tianming Ni
Xiaoqing Wen

Abstract

With the advancement of semiconductor technologies, nano-scale CMOS circuits have become more vulnerable to soft errors, such as single-node-upsets (SNUs) and double-node-upsets (DNUs). In order to effectively tolerate DNUs caused by radiation and reduce the delay and area consumption of latches, this paper proposes a DNU resilient latch in the nanoscale CMOS technology. The latch mainly comprises four input-split inverters and four 2-input Celements. Since all internal nodes are interlocked, the latch can recover from all possible DNUs. Simulation results show that, compared with the state-of-the-art DNU self-recovery latch designs, the proposed latch can save 64.51% transmission delay and 56.88% delay-area-power-product (DAPP) on average, respectively.
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Dates and versions

lirmm-03770815 , version 1 (06-09-2022)

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Cite

Aibin Yan, Zhen Zhou, Shaojie Wei, Jie Cui, Yong Zhou, et al.. A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology. GLVLSI 2022 - 32nd ACM Great Lakes Symposium on VLSI, Jun 2022, Irvine, CA, United States. pp.255-260, ⟨10.1145/3526241.3530321⟩. ⟨lirmm-03770815⟩
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