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Conference Poster Year : 2022

A Performance Evaluation of a Fault-tolerant RISC-V with Vector Instruction Support to Space Applications


Computational systems used in space systems have constantly been evolving in several aspects, ranging from the ability of tolerate faults and failures to process large volumes of data. These aspects mainly affect the characteristics of the processing cores, ranging from microcontrollers to microprocessors, impacting in the computer architecture and organization used. One instruction set architecture under extensive study for application in the space environment is the RISC-V. This architecture has been widely used in space systems because it is simple, open, and modular, enabling the application of techniques that mitigate faults caused in a space environment. How- ever, the application of these techniques affects the performance of the components. Thus, it affects the high-resolution data captured by the sensors, which needs to be processed before being transmitted to Earth. Therefore, it is necessary to apply tech- niques that accelerate the processing of this data. As a solution to the demand for an increase in processing performance, RISC-V can support vector instructions, which allow operating on a vector of data with only one instruction. This approach allows exploring levels of data parallelism and improving the acceleration of applications. Therefore, we developed support for a subset of the vector extension for an existing functional fault-tolerant RISC-V processor. We analyzed the vector instructions that are relevant to digital signal processing, since it is a time-costly type of processing, to define the instructions that constitute the subset. Thus, we implemented only sequen- tial memory access, addition, and subtraction vector instructions. We evaluated the impact of using these instructions compared to scalar instructions, analyzing the exe- cution time, logical resource utilization, and power consumption. The results showed a performance improvement of up to 4x when using the vector instructions relative to the scalar instructions, but, there was a hardware overhead of 1.5x for consumed Lookup Tables and 1.8x for Flip-Flop. Besides the hardware overhead, this cost is negligible compared to the acceleration offered.
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lirmm-03834121 , version 1 (28-10-2022)


  • HAL Id : lirmm-03834121 , version 1


Carolina Imianosky, Douglas Almeida dos Santos, Douglas Rossi de Melo, Luigi Dilillo, Cesar Albenes Zeferino, et al.. A Performance Evaluation of a Fault-tolerant RISC-V with Vector Instruction Support to Space Applications. LASSS/LACW 2022 - Joint 3rd IAA Latin American Symposium on Small Satellites and 5th IAA Latin American CubeSat Workshop, Nov 2022, Brasilia, Brazil. , 2022. ⟨lirmm-03834121⟩
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