A Low Overhead and Double-Node-Upset Self-Recoverable Latch
Abstract
With the rapid advancement of semiconductor technologies, integrated circuits, especially storage elements (e.g., latches) have become increasingly vulnerable to soft errors. In order to effectively tolerate double-node-upsets (DNUs) caused by radiation and reduce the delay and area of latches, this paper proposes a DNU self-recoverable latch with low overhead in terms of power and area. The proposed latch mainly comprises seven 2-input C-elements and two inverters to achieve DNU self-recovery. Simulation results show that the proposed latch can recover from all possible DNUs and that it can reduce delay by 45.71%, power by 29.13%, area by 65.93%, and areapower-delay-product by 87.42% on average compared to typical existing DNU self-recoverable latches.
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