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Conference Papers Year : 2023

Design of Low-Cost Approximate CMOS Full Adders

Aibin Yan
Shaojie Wei
  • Function : Author
  • PersonId : 1161771
Jie Cui
Zhengfeng Huang
Xiaoqing Wen

Abstract

Many applications have an inherent tolerance for insignificant inaccuracies. Full adders are key arithmetic functions for many error-tolerant applications. Approximate full adders are considered an efficient technique to trade off energy relative to performance and accuracy. In this paper, we propose four approximate full adders with low overhead. The proposed and the existing approximate full adders are classified into two groups according to their error distances. Simulation results show that, compared with the existing approximate full adders, in the first group, the proposed ones can reduce power-area-delay product (PADP) by 61.83%, power by 54.15%, area by 44.67%, and delay by 22.78 % on average; in the second group, the proposed ones can reduce PADP by 97.01%, power by 93.43%, area by 24.98%, and delay by 36.14% on average.
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Dates and versions

lirmm-04241285 , version 1 (13-10-2023)

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Aibin Yan, Shaojie Wei, Zhixing Li, Jie Cui, Zhengfeng Huang, et al.. Design of Low-Cost Approximate CMOS Full Adders. ISCAS 2023 - IEEE International Symposium on Circuits and Systems, May 2023, Monterey, CA, United States. ⟨10.1109/ISCAS46773.2023.10181531⟩. ⟨lirmm-04241285⟩
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