A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2023

A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications

Aibin Yan
Tianming Ni
Jie Cui
Xiaoqing Wen

Abstract

In this paper, we propose a double-node-upset recoverable latch that can completely recover from all possible double-node-upsets (DNUs) with low area and low delay. The latch consists of seven 2-input C-elements (CEs) implemented in 22nm complementary metal oxide semiconductor (CMOS) technology, making it area-efficient. The proposed latch employs the clock gating methodology and a high-speed transmission path, enabling it to perform with lower overhead in terms of transmission delay and power dissipation. Simulation results demonstrate that the proposed latch can provide complete DNU recovery. Compared with typical double-node-upset-recoverable latches, the proposed latch can save 89.74% of Area-Delay-Power Product (ADPP) on average.
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Dates and versions

lirmm-04241408 , version 1 (13-10-2023)

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Aibin Yan, Shaojie Wei, Jinjun Zhang, Tianming Ni, Jie Song, et al.. A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications. GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI, Jun 2023, Knoxville, TN, United States. pp.167-171, ⟨10.1145/3583781.3590281⟩. ⟨lirmm-04241408⟩
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