As a consequence of the tremendous rapid pace of semiconductor technology evolution over the last decades, most semiconductor companies have become fabless and outsource the manufacturing step of their designs to offshore foundries. Furthermore, most integration companies rely on Intellectual Property (IP) modules purchased from third parties. Consequently, new threats have arisen such as reverse engineering, IP theft, Integrated Circuits (ICs) overproduction, hardware Trojan insertion, to name just a few. Taking these trust issues into account at design time has therefore become mandatory for protecting IPs despite this new ecosystem. Logic locking is one of these so-called Design-for-Trust approaches. It involves inserting extra key-gates controlled by a secret key in a design so that the manufactured ICs behave correctly only when the correct key value is provided, and erroneously otherwise. This paper introduces a novel key-gate based on tristate logic. The primary goal here is to demonstrate its capability to provide optimal output corruption on circuit outputs when the circuit is not controlled by the correct key value. The paper also provides discussion on protection against the most common attacks developed on current logic locking solutions.