Producing a Bidirectional ATPG Compliant Verilog-HDL Memory Model of SRAM Memory
Abstract
This paper proposes a methodology to produce a digital Verilog-HDL netlist of an SRAM memory, based on an initial SPICE model. The digital model considers the bidirectional nature of the memory, and is ATPG-compliant, allowing the generation of test patterns, and fault simulation.
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