It is well recognized that designs based on automated standard cell flow have been found slower and larger in area than comparable designs manually generated or optimized. On the other hand it becomes necessary for designers to quickly prototype IP blocks in newly available processes. This paper describes an approach combining a performance optimization by path classification (POPS) tool with a transistor level layout synthesis tool (I2P2) dedicated to CMOS synchronous design fast generation. Validations are given on a 0.18 μm CMOS process by comparing standard cell approach to the proposed approach.