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Interconnect Capacitance Modelling in a VDSM CMOS Technology

David Bernard 1 Christian Landrault 2 Pascal Nouet 2 
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper introduces a set of analytical formulations for 3D modelling of inter- and intra-layer capacitance. Based on real silicon data, we have developed and validated efficient and accurate analytical models that are an helpful alternative to lookup tables or numerical simulations.
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Submitted on : Tuesday, October 4, 2022 - 5:12:53 PM
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David Bernard, Christian Landrault, Pascal Nouet. Interconnect Capacitance Modelling in a VDSM CMOS Technology. SOC Design Methodologies, 90, Kluwer Academic Publishers, pp.133-144, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_12⟩. ⟨lirmm-00268482⟩

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