Interconnect Capacitance Modelling in a VDSM CMOS Technology

David Bernard 1 Christian Landrault 2 Pascal Nouet 2
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper introduces a set of analytical formulations for 3D modelling of inter- and intra-layer capacitance. Based on real silicon data, we have developed and validated efficient and accurate analytical models that are an helpful alternative to lookup tables or numerical simulations.
Type de document :
Communication dans un congrès
VLSI-SoC: Very Large Scale Integration of Systems-on-Chip, 2002, Montpellier, France. Kluwer Academic Publishers, SoC Design Methodologies - International Conference on Very Large Scale Integration of Systems-on-Chip, 90, pp.133-144, 2002, 〈10.1007/978-0-387-35597-9_12〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00268482
Contributeur : Christine Carvalho de Matos <>
Soumis le : mardi 1 avril 2008 - 09:27:29
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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David Bernard, Christian Landrault, Pascal Nouet. Interconnect Capacitance Modelling in a VDSM CMOS Technology. VLSI-SoC: Very Large Scale Integration of Systems-on-Chip, 2002, Montpellier, France. Kluwer Academic Publishers, SoC Design Methodologies - International Conference on Very Large Scale Integration of Systems-on-Chip, 90, pp.133-144, 2002, 〈10.1007/978-0-387-35597-9_12〉. 〈lirmm-00268482〉

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