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A New Scan-BIST Structures to Test delay Faults in Sequential Circuits

Patrick Girard 1 Christian Landrault 1 Véronique Moreda 1 Serge Pravossoudovitch 1 Arnaud Virazel 1 
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Delay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test.
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Submitted on : Sunday, March 20, 2022 - 9:03:27 AM
Last modification on : Thursday, August 11, 2022 - 4:04:22 PM
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Patrick Girard, Christian Landrault, Véronique Moreda, Serge Pravossoudovitch, Arnaud Virazel. A New Scan-BIST Structures to Test delay Faults in Sequential Circuits. Journal of Electronic Testing: : Theory and Applications, Springer Verlag, 1999, 14, pp.95-102. ⟨10.1023/A:1008305507376⟩. ⟨lirmm-00345797⟩



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