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A New Scan-BIST Structures to Test delay Faults in Sequential Circuits

Abstract : Delay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00345797
Contributor : Arnaud Virazel <>
Submitted on : Wednesday, December 10, 2008 - 9:19:05 AM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM

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  • HAL Id : lirmm-00345797, version 1

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Patrick Girard, Christian Landrault, Véronique Moreda, Serge Pravossoudovitch, Arnaud Virazel. A New Scan-BIST Structures to Test delay Faults in Sequential Circuits. ETW: European Test Workshop, May 1998, Barcelona, Spain. pp.44-48. ⟨lirmm-00345797⟩

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