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A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk

Patrick Girard 1 Mohammad Tehranipoor 2 Junxia Ma 2
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 UCONN - University of Connecticut
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Journal articles
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00816589
Contributor : Patrick Girard <>
Submitted on : Monday, April 22, 2013 - 3:22:54 PM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM

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  • HAL Id : lirmm-00816589, version 1

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CNRS | SYSMIC | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER

Citation

Patrick Girard, Mohammad Tehranipoor, Junxia Ma. A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk. Journal of Electronic Testing, Springer Verlag, 2012, 28 (2), pp.201-214. ⟨lirmm-00816589⟩

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