A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Journal Articles Journal of Electronic Testing: : Theory and Applications Year : 2012

A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk

Patrick Girard
Conception et Test de Systèmes MICroélectroniques
CV
Mohammad Tehranipoor
  • Function : Author
University of Connecticut
Junxia Ma
  • Function : Author
  • PersonId : 940567
University of Connecticut

Domains

Micro and nanotechnologies/Microelectronics

Patrick Girard  : Connect in order to contact the contributor

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00816589

Submitted on : Monday, April 22, 2013-3:22:54 PM

Last modification on : Friday, March 24, 2023-2:52:57 PM

Consult on ISTEX platform

Dates and versions

lirmm-00816589 , version 1 (22-04-2013)

Identifiers

Cite

Patrick Girard, Mohammad Tehranipoor, Junxia Ma. A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk. Journal of Electronic Testing: : Theory and Applications, 2012, 28 (2), pp.201-214. ⟨10.1007/s10836-011-5268-x⟩. ⟨lirmm-00816589⟩

Export

BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite

Collections

CNRS SYSMIC LIRMM LIRMM_MIC MIC MIPS UNIV-MONTPELLIER
58 View
0 Download

Altmetric

Share

More