Performance exploration of partially connected 3D NoCs under manufacturing variability

Abstract : Several Through-Silicon-Vias (TSVs) may present resistive and open defects due to 3D manufacture variability. This paper advocates the use of 3D Network-on-Chip (NoC) with asynchronous communication interfaces to cope with significant variations in TSV propagation delays. The technique uses serial communication in the vertical channels to reduce the number of TSVs. Based on a representative delay distribution, we compare the average performance considering a non-defective 3D NoC, one with resistive defective TSVs and one with resistive and open defective TSVs. Results show that it is better to adapt the interfaces to cope with large margins of delay than to avoid TSVs by using adaptive routing.
Type de document :
Communication dans un congrès
NEWCAS: International New Circuits and Systems Conference, Jun 2014, Trois-Rivieres, QC, Canada. IEEE, New Circuits and Systems Conference (NEWCAS), 2014 IEEE 12th International, pp.61-64, 2014, 〈10.1109/NEWCAS.2014.6933985〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01248595
Contributeur : Aida Todri-Sanial <>
Soumis le : dimanche 27 décembre 2015 - 21:41:30
Dernière modification le : samedi 10 février 2018 - 07:52:02

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Anelise Kologeski, Fernanda Lima Kastensmidt, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, et al.. Performance exploration of partially connected 3D NoCs under manufacturing variability. NEWCAS: International New Circuits and Systems Conference, Jun 2014, Trois-Rivieres, QC, Canada. IEEE, New Circuits and Systems Conference (NEWCAS), 2014 IEEE 12th International, pp.61-64, 2014, 〈10.1109/NEWCAS.2014.6933985〉. 〈lirmm-01248595〉

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