Performance exploration of partially connected 3D NoCs under manufacturing variability
Abstract
Several Through-Silicon-Vias (TSVs) may present resistive and open defects due to 3D manufacture variability. This paper advocates the use of 3D Network-on-Chip (NoC) with asynchronous communication interfaces to cope with significant variations in TSV propagation delays. The technique uses serial communication in the vertical channels to reduce the number of TSVs. Based on a representative delay distribution, we compare the average performance considering a non-defective 3D NoC, one with resistive defective TSVs and one with resistive and open defective TSVs. Results show that it is better to adapt the interfaces to cope with large margins of delay than to avoid TSVs by using adaptive routing.
Keywords
Resistive defective TSV
Delay variation
TSV propagation delays
Open defective TSV
TSVs
Through-silicon vias
Integrated circuit manufacture
Three-dimensional integrated circuits
Network routing
Three-dimensional displays
Fault tolerance
Manufacturing variability
Telecommunication traffic
Serialization
Asynchronous communication interfaces
Delay distribution
Partially connected 3D NoC
Partially asynchronous 3D NoCs
Yield
Routing
Elevators
Clocks
Delays
Network-on-chip
Serial communication
3D network-on-chip
Adaptive routing
3D manufacture variability