Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs

Abstract : This work investigates the effects of aging and voltage scaling in neutron-induced bit-flip in SRAM-based FPGAs. Experimental results show that aging and voltage scaling can increase in at least two times the susceptibility of SRAM-based FPGAs to Soft Error Rate (SER). These results are innovative, because they combine three real effects that occur in programmable circuits operating at ground-level applications. In addition, a model at electrical simulation for aging, soft error and different voltages was described to investigate the effects observed at the practical neutron irradiation experiment. Results can guide designers to predict soft error effects during the lifetime of devices operating in different power supply mode.
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Communication dans un congrès
ETS: European Test Symposium, May 2014, Paderborn, Germany. 19th IEEE European Test Symposium, 2014, 〈10.1109/ETS.2014.6847845〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01421128
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Dernière modification le : jeudi 11 janvier 2018 - 06:27:19
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Fernanda Lima Kastensmidt, Jorge Tonfat, Thiago Both, Paolo Rech, Gilson Wirth, et al.. Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs. ETS: European Test Symposium, May 2014, Paderborn, Germany. 19th IEEE European Test Symposium, 2014, 〈10.1109/ETS.2014.6847845〉. 〈lirmm-01421128〉

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