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Reports (Research Report) Year : 2017

Deliverable D2.2 – Description of a specific optimization for low power

Abstract

While emerging non-volatile memories are a promising low power design solution for modern architectures, they suffer from high write-latency and energy consumption. This makes them less favorable for first-level caches such as L1 cache, compared to usual SRAM memory. We propose a compiler-based approach to attenuate the cost of write operations in an architecture that integrates magnetic memory such as the Spin Transfer Torque Random Access Memory (STT-RAM) technology for L1 cache. In this deliverable, we present an LLVM optimization to reduce the number of silent stores in memory (stores that have no impact because they write a value already present in memory at this location), therefore mitigating the number of write transactions on STT-RAM memory. We show our recent results that confirm the promising impact of this optimization on energy consumption. We also analyze in details the impact of the application characteristics, the compiler, and various microarchitectural features.
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Dates and versions

lirmm-03168308 , version 1 (12-03-2021)

Identifiers

  • HAL Id : lirmm-03168308 , version 1

Cite

Rabab Bouziane, Erven Rohou, Abdoulaye Gamatié. Deliverable D2.2 – Description of a specific optimization for low power. [Research Report] Inria Rennes - Bretagne Atlantique; LIRMM (UM, CNRS). 2017. ⟨lirmm-03168308⟩
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