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Fast Cycle-approximate Simulation Techniques for Manycore Architecture Exploration

Anastasiia Butko 1
1 ADAC - ADAptive Computing
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Since the computational needs precipitously grow each year, HPC technology becomes a driving force for numerous scienti fic and consumer areas. The most powerful supercomputer has been progressing from TFLOPS to PFLOPS throughout the last ten years. However, the extremely high power consumption and therefore the high cost pushed researchers to explore more energy-efficient technologies, such as the use of low-power embedded SoCs. The evolution of emerging manycore systems forecasted to feature hundreds of cores by the end of the decade calls for efficient solutions for the design space exploration and debugging. Available industrial and academic simulators diff er in terms of simulation speed/accuracy trade-off s. Cycle-approximate simulators are popular and attractive for architectural exploration. Even though enabling flexible and detailed architecture evaluation, cycle-approximate simulators entail slow simulation speeds, thereby limiting their scope of applicability for systems with hundreds of cores. This calls for alternative approaches capable of providing high simulation speed while preserving accuracy that is crucial to architectural exploration. In this thesis, we evaluate cycle-approximate simulation techniques for fast and accurate exploration of multi- and manycore architecture exploration. Expecting to significantly reduce simulation time still preserving the accuracy at the cycle-approximate level, we propose a hybrid trace-oriented approach to enable flexible manycore architecture simulation. We design a set of simulation techniques to overcome the main weaknesses of the trace-oriented approach. The trace synchronization technique aims to manage control and data dependencies arising from the abstraction of processor cores. The trace replication technique is proposed to simulate manycore architectures using a finite set of pre-collected traces. The computation phase scaling technique is designed to enable flexible switching between multiple processor models without considering microarchitectural diff erence but taking into account the computation speed ratio. Based on the proposed simulation environment, we explore several manycore architectures in terms of performance and energy-efficiency trade-o ffs.
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Submitted on : Tuesday, December 18, 2018 - 1:57:56 PM
Last modification on : Wednesday, June 26, 2019 - 1:47:25 AM
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  • HAL Id : tel-01959029, version 1



Anastasiia Butko. Fast Cycle-approximate Simulation Techniques for Manycore Architecture Exploration. Embedded Systems. Universitté de Montpellier, 2015. English. ⟨NNT : 2015MONTS144⟩. ⟨tel-01959029v1⟩



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