Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Journal Articles Microprocessors and Microsystems: Embedded Hardware Design Year : 2015

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

Abstract

Advanced computing systems realized in forthcoming technologies hold the promise of a significant increase of computational capabilities. However, the same path that is leading technologies toward these remarkable achievements is also making electronic devices increasingly unreliable. Developing new methods to evaluate the reliability of these systems in an early design stage has the potential to save costs, produce optimized designs and have a positive impact on the product time-to-market.
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lirmm-01297595 , version 1 (04-04-2016)

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Alessandro Vallero, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Maha Kooli, et al.. Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview. Microprocessors and Microsystems: Embedded Hardware Design , 2015, 39 (8), pp.1204-1214. ⟨10.1016/j.micpro.2015.06.003⟩. ⟨lirmm-01297595⟩
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