Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology Nodes

Abstract : This paper presents a design and methodology for accurate characterization of setup and hold margins in silicon while taking into account effects of Process Variations (PV). The test circuit provides deeper insights into sources of extra timing margins available on silicon. This in turn, enables accurate guard banding by preventing optimism and reducing unnecessary pessimism in the timing margins provided during sign-off. Our design has been used for the development of the 28nm Fully Depleted Silicon On Insulator (FDSOI) node and associated relevant results and analysis have been provided.
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Communication dans un congrès
ISQED: International Symposium & Exhibits on Quality Electronic Desgn, Mar 2016, Santa Clara, CA, United States. 17th International Symposium & Exhibits on Quality Electronic Desgn, pp.295-300, 2016, 〈http://www.isqed.org/English/Archives/2016/index.html〉. 〈10.1109/ISQED.2016.7479217〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01433314
Contributeur : Arnaud Virazel <>
Soumis le : jeudi 12 janvier 2017 - 15:47:44
Dernière modification le : jeudi 24 mai 2018 - 15:59:25

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Deepak Kumar Arora, Darayus Adil Patel, Nc Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, et al.. Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology Nodes. ISQED: International Symposium & Exhibits on Quality Electronic Desgn, Mar 2016, Santa Clara, CA, United States. 17th International Symposium & Exhibits on Quality Electronic Desgn, pp.295-300, 2016, 〈http://www.isqed.org/English/Archives/2016/index.html〉. 〈10.1109/ISQED.2016.7479217〉. 〈lirmm-01433314〉

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