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Conference Papers Year : 2016

Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology Nodes

Abstract

This paper presents a design and methodology for accurate characterization of setup and hold margins in silicon while taking into account effects of Process Variations (PV). The test circuit provides deeper insights into sources of extra timing margins available on silicon. This in turn, enables accurate guard banding by preventing optimism and reducing unnecessary pessimism in the timing margins provided during sign-off. Our design has been used for the development of the 28nm Fully Depleted Silicon On Insulator (FDSOI) node and associated relevant results and analysis have been provided.
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lirmm-01433314 , version 1 (12-01-2017)

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Deepak Kumar Arora, Darayus Adil Patel, Nc Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, et al.. Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology Nodes. ISQED 2016 - 17th International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. pp.295-300, ⟨10.1109/ISQED.2016.7479217⟩. ⟨lirmm-01433314⟩
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