Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology Nodes

Deepak Kumar Arora 1 Darayus Adil Patel 2, 3 Nc Shahabuddin 1 Sanjay Kumar 1 Navin Kumar Dayani 1 Balwant Singh 1 Sylvie Naudet 2 Arnaud Virazel 4 Alberto Bosio 4
3 TEST - TEST
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
4 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper presents a design and methodology for accurate characterization of setup and hold margins in silicon while taking into account effects of Process Variations (PV). The test circuit provides deeper insights into sources of extra timing margins available on silicon. This in turn, enables accurate guard banding by preventing optimism and reducing unnecessary pessimism in the timing margins provided during sign-off. Our design has been used for the development of the 28nm Fully Depleted Silicon On Insulator (FDSOI) node and associated relevant results and analysis have been provided.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01433314
Contributor : Arnaud Virazel <>
Submitted on : Thursday, January 12, 2017 - 3:47:44 PM
Last modification on : Wednesday, May 8, 2019 - 2:56:01 PM

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Deepak Kumar Arora, Darayus Adil Patel, Nc Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, et al.. Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology Nodes. ISQED: International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. pp.295-300, ⟨10.1109/ISQED.2016.7479217⟩. ⟨lirmm-01433314⟩

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